Certain processes for transferring the layer of relaxed material grown epitaxially on a buffer layer from the wafer on to a receiving substrate are known. Such processes are, for example, disclosed in an IBM article by L. J. Huang et al. (“SiGe-On-Insulator prepared by wafer bonding and layer transfer for high-performance field-effect transistors”, Applied Physics Letters, 26 Feb. 2001, Vol. 78, No. 9) and in PCT patent application WO 02/33746, in which documents an SGOI (Silicon-Germanium-On-Insulator) structure is produced from a wafer comprising in succession a single-crystal Si support substrate, an SiGe buffer layer and a relaxed SiGe layer.
The process employed by L. J. Huang et al. consists in carrying out the SMART-CUT® process of SOITEC, one which is generally known to those skilled in the art, and descriptions of which may be found in a number of works dealing with wafer reduction techniques, in order to remove the relaxed SiGe layer so as to transfer it by means of bonding on to an oxidized receiving substrate, thus producing an SGOI structure. Despite the advantages that this process affords, the surface of the transferred layer may have a roughness that requires a surface finishing step. This finishing step is generally carried out by means of CMP (chemical-mechanical polishing or chemical-mechanical planarization), which may create surface defects (such as strain-hardened regions), which may imperfectly correct the thickness, and thus retain inhomogeneous layer thicknesses, and which may slow down the transfer of the SiGe layer, and increase its cost.
The process disclosed in PCT application WO 02/33746 includes, in addition to a CMP polishing step, preliminary lapping, polishing and etching steps in order to remove part of the wafer, thereby slowing down the overall process of removal from the wafer and increasing its cost even further, while not ensuring good homogeneity in layer thickness. To try to alleviate this, U.S. Pat. No. 5,882,987 and an article by K. D. Hobart et al. from the Naval Research Laboratory in Washington (“On scaling the thin film Si thickness of SOI substrates”) both disclose an overall process for producing SOI (silicon-on-insulator) structures from a wafer comprising in succession a single-crystal Si support substrate, an SiGe layer and an epitaxially grown Si layer bonded to an oxidized receiving substrate.
The SMART-CUT® technique is employed and causes, after bonding the wafer to a receiving substrate, detachment of part of the wafer at the Si support substrate. A structure consisting in succession of part of the Si support substrate, the SiGe layer and the epitaxially grown Si layer is thus removed, the whole assembly being bonded to the oxidized receiving substrate.
Two successive selective etching operations are then carried out on the structure in order to remove firstly the remaining part of the Si support substrate with an etching solution such that the SiGe layer forms a stop layer and then in order to remove the SiGe layer with an etching solution such that the Si layer forms a stop layer.
The structure obtained at the end is an SOI structure with a surface Si layer. Thus, an SeOI structure is obtained with a semiconductor layer which is both thin and uniform through the thickness, substantially identical to the epitaxially grown initial layer, while avoiding the use of a finishing step other than a selective etching operation. The SiGe layer inserted between the Si wafer and the epitaxially grown Si layer, however, has a typical thickness of between 0.01 and 0.2 microns, a thickness which is insufficient to fulfill the role of a buffer layer between the Si wafer and a potential relaxed SiGe layer. The wafer therefore does not include a buffer layer. In addition, given the order of magnitude of the thickness of the inserted SiGe layer, the structural (strained, relaxed or intermediate) state of the latter does not seem defined with certainty.
PCT patent application WO 01/99169 discloses processes for producing, from a wafer consisting in succession of an Si substrate, an SiGe buffer layer, a relaxed SiGe layer and optionally a strained Si or SiGe layer, a final structure with the relaxed SiGe layer on the optional other strained Si or SiGe layer. The technique employed for producing such a structure involves, after bonding the wafer to a receiving substrate, removal of the material of the wafer that it is desired not to retain, by selectively etching the Si substrate and the SiGe buffer layer. Although this technique does make it possible to achieve particularly small layer thicknesses which are homogeneous through the thickness, it entails destruction of the Si substrate and the SiGe buffer layer by chemical etching. These processes therefore do not allow the possibility of reusing part of the wafer, and especially at least part of the buffer layer, for a further transfer of layers.
A method for transferring a semiconductor wafer with high quality, smooth and uniform, surface is thus desired, preferably which can be reused for transferring further layers.